Today Static memories are one of important parts of digital circuits and due to appropriate speed and power are used to build embedded memories which are the SOC vital parts. Static memories are also used to create caches. With increased demand for battery driven applications, methods for reduce power consumption in the memory blocks receive special attention. Static memory cells are in hold mode most of the times, in addition when Static memory size becomes large, Static power will become significant and the most of power consumption will belong to it. Thus reduce Static power becomes a priority. In this paper, a new low power SRAM with ability to separate read and write path is presented. The Static power of proposed structure is reduced 78. 21% than the conventional six-transistor cell, and read Static noise margin is enhanced 202. 59% rather than the conventional six-transistor cell. In order to evaluate the performance of the proposed cell and comparing the results, simulations are done in TSMC 130nm CMOS technology and the supply voltage of 1. 2 V.

Three new SRAM cells are proposed in this paper. Increasing area overhead is the major concern in SRAM design.One of the new structures is included four transistors instead of six transistors as it is used in conventional 6T-SRAM cell for very high density embedded SRAM applications. The structure of proposed SRAM employs one word-line and one bit-line during Read/Write operation. The new SRAM cell has smaller size, leakage current and power dissipation in contrast of a conventional six transistor SRAMs. A proposed 4T-SRAM cell has been simulated for 256 cells per bit-line and 128 columns cell for supply voltage of 1.2V. Furthermore, two other new structures are included 10 and 11 transistors. These new structures have been separate read and write process by changing in the structure of conventional 6T SRAM to achieve high Static noise margin (SNM). Using 10T and 11T SRAM cells lead to apply 512 cells per bit-line by reducing leakage current technique, while the cell is unavailable.128 columns cell array has been built to measure the operation of SRAM cell. To have low power dissipation, the supply voltage for 10T and 11T are chosen 0.32V and 0.27V, respectively. Proposed SRAM uses one read bit-line during read operation. Simulation results have been confirmed by HSPICE in 0.13um process.

This paper presents analysis of the Static noise margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T Static Random Access Memory (SRAM) cell for read operations. In the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for the read Static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in dierent literatures. It is shown that the proposed SRAM cell has better Static noise margin and dissipates less power in comparison to other SRAM cells. Analog and schematic simulations have been done in a 45 nm environment with the help of Microwind 3.1, using the BSimM4 model.

Ship interior noise produced by engine room disturbs the crews and the workers. Also, it causes lots of complications for the crews and the passengers in the ship. Active noise cancellation (ANC) is based on the destructive interference between the primary noise and generated noise from the secondary source. In this research, performance of the Static and dynamic neural networks is evaluated in active cancellation of sound noise. For this reason, MLP and RBF are designed and trained as Static neural networks. After training, performance of Static and dynamic networks in noise attenuation are compared. In order to compare the networks appropriately, training and test samples are similar. Moreover, equal number of layers and neurons are considered for the networks. noise signals from a SPIB database are used in simulation procedures. The simulation results show that designed neural networks present proper performance in ANC because of using training and validation samples in training process. As it is seen, the trained dynamic network and RBF neural network show better performance in noise attenuation than MLP network and achieve 1 dB noise attenuation more than MLP network.

This paper proposes an enhanced replacement policy to mitigate the coherence-induced vulnerability of cache memories by Static noise margin degradation prevention. The enhancement is conducted based on the outcomes of a comprehensive study intended to investigate the causes of Static noise margin degradation in the SRAM cells. The empirical analysis demonstrates that the unbalanced distribution of data blocks associated with different coherency states over lines of a cache set can also be interpreted as a cause of the Static noise margin degradation. Based on the findings, an aging-aware cache replacement policy is presented to balance the distribution of dirty/clean data blocks over the cache lines. To this intent, the decision tree of the Pseudo-LRU is revisited concerning the coherency state of cache lines and the type of address conflict miss. Using the enhanced cache, the hold and read Static noise margin degradation are improved by about 9.9% and 11.5%, with less than 1.0% reduction in the cache hit ratio and negligible area and energy overheads.

Nano scale statistical variability which arises from discreteness of charge and granularity of matter has become one of major concerns in digital design particularly in sub-50nm technology nodes. Device intrinsic parameters such as the threshold voltage and drive current will be influenced by random dopants, line edge roughness and gate grain granularity which in turn results in variation of SRAM cell performance. Therefore, providing an accurate statistical model is one of the key issues among SRAM design community. Since both 6T and 8T SRAMs are widely used in the industry as standard cells, this article analyzes sensitivity of Static noise margin (SNM) in response to statistical variations in 6- and 8-transistor cells. The results show that though 8T cells need more transistors and thus consume more area on the wafer compared with 6T cells, they are more stable and thus are better candidates for variability aware design in future technology nodes.

In this paper, the Static Var Compensator (SVC) has been used to improve dynamic behaviour of power system. To do this, a new objective function is formulated considering power loss reduction, voltage profile improvement and loadability margin decrease. Other contribution of this research is proposing a novel structure for Particle Swarm Optimization (PSO) algorithm through modifying the initialization pattern of constant parameters. IEEE 33-bus test system has been simulated applying this method and by comparing the results with corresponding values of simple PSO algorithm, capability of the proposed algorithm is approved. Eight parameters are surveyed to have a thorough comparison which are number of SVC, injected reactive power, angle and magnitude of voltage, loadability, power loss, objective function and optimal location and size of SVC.